Planning and Process for Integrated Circuit Electrostatic Protection and Latch-Up Testing

Every product has a service life. In other words, it is possible to get an idea of how reliable a product is. If it can be used for several years or at least last until the release of the next generation of products, it can be said that a product has good reliability. Accordingly, if the time of use does not reach the level that the product should have then its reliability is poor. So how do we measure the reliability of a product? Basically, we can estimate a product’s service life by taking the conditions of the use environment, such as the voltage, temperature, humidity and any other unfavorable environmental factors, and substituting them into the appropriate failure model.

In the environment we live in, static electricity is a ubiquitous assassin. Since static electricity cannot be completely prevented, we must consider how to help the product escape unscathed after a charge flows through the integrated circuit. To this end, IC designs generally include Electrostatic Discharge (ESD) protection circuits next to the pins to protect the chips. This is much like placing a lightning rod on top of a building to divert lightning when it strikes in order to ensure that the electrical appliances in the building are not damaged. In addition, due to the characteristics of the structure of these components, the Latch-Up (LU) effect can cause large currents to flow through integrated circuits during operation, resulting in problems with functionality. It may even cause permanent damage to the chip. Therefore, the chip’s design also needs to take the prevention of LU-related problems into account.

In order to verify ESD and LU protection capabilities, the first task is to determine how to use the specialized testing instruments and follow the regulations and procedures defined by international standards to confirm the reliability of the integrated circuits. If the circuit component fails to pass the ESD and LU tests and the reason for the failure has been identified, the second task is to determine how to enhance the chip design. This article focuses on these two tasks and explains the preparations and related judgment criteria that come before ESD and LU testing and the subsequent processes for analyzing the true causes of problems.

Prior to conducting the first ESD and LU tests, common problems encountered include how to plan and execute the tests and how to communicate these test plans with the project manager. In order to improve the efficiency of communication between the relevant parties, consider providing information based on the following topics.

Before conducting the test, it is important to set the international standards and specifications to be used. The theoretical foundation of these specifications is what gives the ESD/LU tests their credibility, enabling customers to trust the usage guarantees signified by passing these verifications. The following are different test items and their corresponding international standards and specifications.

1. HBM:

• MIL-STD: Component Types and Certain Driver ICs

• AEC-Q100 or AEC-Q101: Automotive Qualifications

• JEDEC: Other Consumer Product Verifications

    2. CDM:

• ANSI/ESD SP5.3.2: These are the SCDM test specifications. At present, only a handful of driver IC customers will request the SCDM test.

• AEC-Q100 or AEC-Q101: Vehicle Certification

• JEDEC: The old JESD22-C101F and the new JS-002-2022 specifications are used mostly for JEDEC-type consumer products. Customers are advised to follow the most recent  JS-002-2022.

    3. LU:

• JESD78F: Consumer Products

• AEC-Q100: Vehicle Certification

• HBM: It is recommended to start with 500V then move on to 1KV, 2KV, 4KV, and 8KV.

• CDM: The JEDEC safety standard is 500V. The AEC-Q100 also includes corner pins with an increased standard of 750V (Figure 1). It is recommended that voltage tests are conducted in steps going from 250V to 500V, 750V then 1000V.

• LU: Generally, the specifications ask only that the signal pin be +100mA /-100mA. The power pin is set at 1.5*VDDmax. In the industry, however, it is customary to test a level higher, going up to 200mA. The rated voltage and limit values must also be provided in order to set the operating conditions.

HBM /CDM / LU: The specifications require data on 3 samples for each test condition.

It is necessary to provide the name, pin-type (Input / Output / IO / Power / GND) and position of test pins to facilitate the evaluation of the analysis time and condition settings. This information also serves as the basis for making test fixtures.

When using MIL-STD specifications, all four test combinations in the first row of Table 1 can be selected. Under these specifications, the power/ground of each power domain can be connected in parallel. When using JEDEC specifications, you have a choice between Table 2A and 2B. In Table 2B, power/ground devices in the same power domain can be connected to each other in parallel, but the power/ground of different power domains are not connected. Under these conditions, all IO pins can apply ESD to different power domains. In Table 2A, the IO pin only applies ESD to its own power/ground. If you want the most stringent test conditions but are unclear on which test combination or vehicle specification verification should be used, it is recommended to use Table 2B. As for the vehicle regulation AEC-Q100 certification, if the number of package pins is equal to or less than six then every arrangement and combination of 2 pins needs to be verified.

Table 1. Row 1 contains the IO and power/ground test combinations; Rows 2 and 3 are the specifications to be adopted.

The goal of LU testing is to determine whether there is abnormal signal interference that might excite large currents. Therefore, after considering the test conditions to be set and what might actually happen in the environment, some customers choose specific conditions for LU testing, as described below.

At high temperatures, the increase in leakage can easily trigger the parasitic silicon controlled rectifier (SCR) and cause the LU effect. Therefore, you can choose two test environments: normal temperature and high temperature (which depends on the maximum operating temperature, or  Tj  temperature, of the product specifications). The AEC mandates high temperature testing.

High performance computing (HPC) ICs tend to have a higher Quiescent Current. The market share of this type of IC is gradually increasing, and existing LU testing equipment can no longer meet the high current requirements. As such, High Current LU equipment and external high-power measuring instruments need to be customized separately.

Typically, the IC LU test is a static test, meaning that the input voltage and current are fixed values. However, actual IC operation is dynamic, and the input and output pins will experience periodic changes in their high and low voltages. Therefore, the LU test’s pattern input is meant to simulate real LU behavior under dynamic IC input.

HBM and CDM specifications require comprehensive testing, which includes Parametric Testing and Functional Testing. This is the only way to ensure that failures caused by ESD damage can be caught. In terms of parameter testing, Open/Short (OS), leakage and the quiescent current at the Power terminal are tested using the automatic test machine (ATE). However, if you use an ESD testing machine, there are two ways to measure and compare the difference before and after the ESD test in real time. The first is to measure whether the difference in voltage when the current is equal to 1uA before and after the test is less than 30%. If so then it passes the ESD test, as shown in Figure 2. The second approach is the Curve Compare Envelope. For this method, use the IV curve before ESD testing as a reference and use plus/minus 10% of the maximum tested voltage and current  as the adjustment value. Add this adjustment value to the IV Curve before testing to get an interval. As long as the tested IV is within this range, it passes the ESD verification, as shown in Figure 3.

Figure 2. IV Changes Before and After Zap; If the change in voltage at 1uA is more than 30%, this Pin Fails the ESD verification.

Figure 3. Schematic Diagram of the Curve Compare Envelope; If the IV curve after zap exceeds the range indicated by the green line, this pin fails the ESD verification.

Whether or not the LU verification is passed is determined by the current before measurement. If the current before measurement is  INOM, then if the maximum value is less than either 1.4xINOM or INOM+10mA (whichever is greater) then the verification is passed.

According to ESD failure principles and past examples, when the overcurrent or overvoltage generated by electrostatic discharge exceeds the tolerance of the component, it experiences burnout. The discharge path determines the type of component burnout, such as Junction leakage, Gate Oxide Breakdown, breakdown between the Drain and Source or breakdown between two different components, etc.. If the component’s burn is severe, it will extend upward towards the metal layer. Since this is burn damage, Photon Emission Microscopy (PEM, commonly known as EMMI) is generally a good choice for locating the afflicted area. The OBIRCH, with its ability to detect changes in resistance, can be considered if you need to further confirm the burn location.

The location of electrostatic discharge burns can generally be divided into two categories based on the circuits in which they occur: the ESD circuit (IO Cell) or the internal circuit. When the IO Cell is burned, it can be understood that the ESD circuit diverted the static electricity, preventing it from damaging the internal circuit. However, when the overcurrent exceeds the tolerance of the ESD circuit, it may cause burnout. This type of burnout occurs when there are abnormal Pins in the parameter test. Therefore, burn locations are relatively easy to find.

According to the whole-chip protection theory, when electrostatic discharge does not follow the conductive IO Cell as intended but instead follows the fastest and most fragile path, it may damage the internal circuit. At such times, you must use positioning tools to locate the burned components so that you can understand the discharge path and then improve the design of the discharge path and prevent blockage.

In summary, to ascertain the burned components or circuits, there are the following options:

1. If the damaged circuit is known to be in the IO Cell, you can quickly confirm the location by performing a Total Delayer and then conducting further observation with an optical microscope (OM) or a scanning electron microscope (SEM) as shown in Figure 4.

2. Use the bright spot positioning tools EMMI or OBIRCH to find the components where bright spots are located. In some cases, IC design and development engineers can deduce the ESD failure model based on the components corresponding to the bright spots then make design improvements, as shown in Figure 5.

3. Based on the above, in order to verify the precise failure mechanism, the metal layer can be removed layer by layer until the bottom layer of Contact / Poly / AA  is exposed. The burn can then be observed. Sometimes a special sample preparation method may be needed to confirm the gate oxide pinhole, especially for CDM failure experiments. See Figure 6.

Figure 6. ESD Failure Light Spot Detected on the Logic Circuit Via EMMI

Figure 7. Delayer Layer by Layer to Observe ESD Circuit Burnout

An important goal of the above ESD failure analysis process is to confirm the discharge path. To this end, it is recommended to look for traces of damage in the Plane View. In this way, a model of the electrostatic discharge failure can be established, and dredging or throttling countermeasures can be taken. If dredging, design other conduction paths. For example, more Contacts can be used to reduce Current Density. If throttling, you caon design a current limiting resistor to prevent burnout caused by excessive current.

The LU effect is caused by external inference signals that trigger parasitic SCRs, generating an excessive current which causes problems with functionality. So the first step in LU analysis is to identify where the parasitic SCR components are. When LU occurs, the excessive current may cause serious burning of the chip. The burn location can easily be found using electrical positioning tools. However, it should be noted that the location of the burn will be the path of the large current, which is not necessarily the location of the parasitic SCR component. Therefore, it is not as easy to find the true cause of the burn.

ESD and LU testing and analysis are an indispensable part of the product development process. Follow the verification process outlined in this article to quickly solve certification issues. If you have other concerns or special circumstances, feel free to contact MA-tek’s professional team for a more in-depth analysis.