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CPU

Intel Pentium D processor 955 Constructional Analysis

Plan-view (P-V) and cross-sectional (X-S) SEM, TEM microscopy were conducted to reveal the circuit layout and material architecture of the devices. TEM / EDX analysis were conducted to analyze the constituent of the key regions. SIMS (Secondary Ion Mass Spectrometry) was used to determine the doping profiles of device formation. It contains a microstructure analysis in terms of process technology. The process features were shown as follows.

Two IC chips were found of the same size in the package
The IC architecture was characterized by a 8-level metal, Cu damascene, process. [39.6 nm gate length and 16 Ǻ gate oxide]
W-plug, followed by a global CMP planarization, was conducted as the first level metal contact
Recessed S/D was shown to be resulted from spacer etch
In some region of the chip, selective Si-Ge epitaxial growth was made on active area, where the thickness of epitaxial layer was about 931 Ǻ
Carbon containing Low-K oxide was found in ILD and IMD layers

1-1. External inspection of the part – front side and back side

The package marking is：

1．INTEL © ‘05

2．PENTIUM ® D

3．955 SL94N MALAY

4．3.46GHZ / 4M/1 066

5．L541B538

(a) Front-side

(b) Back-side

1.3 Disassembly of the back-side package – remove the plastic cap of the back side

After removing the plastic cover, the back side of PCB was shown to be with metal joints for part mounting.

Back-side of the part

1.5 Examination of IC chips

(a) Package (after chip removal) (b) IC Chips (face up)

It was found two IC chips were mounted on PCB board by flip-chip technology.
Pb-Sn solder bumps were found to be of high density array on chip surface.

1.6 Product number and logo on IC chip

The two chips were of the same size, which were measured to be 9.52 mm x 7.62 mm
The die markings of two chips were also the same, which was shown to be 8PCDCA©intel’05

1.7 Pb-Sn solder bumps on chip surface

Pb-Sn solder bumps were capped with polyimide on chip surface
After removing the polyimide, the solder bumps and metal layout were exposed

(a) Package (after chip removal)

(b) IC Chips (face up)

1.8 SEM/EDX analysis of Pb-Sn solder balls on chip surface

The ball size was estimatedto be 118.1 um in diameter
With the aid of SEM/EDX analysis, the composition of solder bumps was identified to be of Pb-Sn alloy

2.2 Vertical structure of IC architecture – in parallel with poly-gate (M3-M1)

Metal 3 to metal 1are shown in the micrograph. The thickness of layers are shown in the micrograph

3.1 Vertical structure of IC architecture – across poly-gate (M8-STI)

This chip was manufactured to be a 8-level metal, Cu damascene process
The dual-damascene uses the via-first approach
Only the first level metal contact was made by W-plug process
STI (shallow trench isolation) was applied to be the filed isolation

3.2 Vertical structure of IC architecture - across poly-gate direction (M1-poly gate)

It was shown clearly in section 3.1 that M-1 was formed after global planarization by CMP (chemical mechanical polish) of ILD and W-plug
The first level metal contact was made by W-plug, 0.092 µm in diameter and 0.34 µm in height

3.3 Vertical structure of IC architecture - across poly-gate direction (dimension measurement of gate structure)

Vertical dimension of gate structure was shown in the left
Horizontal dimension of gate structure was shown in the right
The minimum channel length was shown to be 39.6 nm
The TEM/EDX analysis results in section 3.4 shows the composition of spacer may be SiC

4.1 The summary table of each materials of vertical structur

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