Advanced Transistor Technologies and Development Trends
Chee Wee Liu, Distinguished Chair Professor
National Taiwan University, Institute of Electronical Engineering
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As traditional semiconductors shrink in size, the gate length of transistors too is shrinking. Semiconductor wafer manufacturing technology is often evaluated based on the gate length of its transistors because the smaller the gate length, the smaller the transistor. Smaller transistors mean that the same size chip can accommodate more transistors. This, in turn, means more functions and better performance. However, in truth, the gate length and the value of the technology node are not equivocal. For technology nodes after the 22 nanometer node, gate lengths are greater than the value of the node (Figure 1). As transistors continue to shrink, traditional scaling methods are gradually approaching their limits. Scaling based solely on Moore’s Law is no longer able to chieve the expected performance growth. Starting with the 22nm technology node (Intel) and the 16nm technology node (TSMC), the industry began adopting the FinFET transistor proposed by Chenming Hu’s research team, and 3D transistors became the mainstream structure of today’s semiconductors. Generally, the naming of today’s process technology nodes usually takes the previous generation’s process size and multiplies by 0.7. This indicates that the area occupied by the transistor is halved, so, on a chip of the same size, the transistor density will be double. However, as processes continue to evolve over time, it is no longer possible to fully evaluate the performance of a chip simply based on its gate length, and various companies are no longer naming processes after it. Therefore, the process sizes commonly seen in today’s news, such as the 3nm and 5nm, are more like indicators representing the progress of technology nodes and the improvement of transistor density rather than actual gate lengths. Transistor size is represented by the CPP (Contact Poly Pitch), which is the sum of the gate length, 2 spacers (2LSP) and the S/D length (Figure 2) [1].
Figure 1: Diagram of the Relationship Between Technology Nodes and Gate Length |
Figure 2: Transistor CPP (Contact Poly Pitch) Schematic Diagram [1] |
In addition to increasing the drive current of transistors, reducing chip power consumption is also an important approach to improving chip computing performance. Reducing chip power consumption would extend the use time of smart mobile devices and improve their battery life. Among the various approaches, reducing the chip operating voltage (VDD) is an effective way to reduce the energy consumption caused by transistor operation. The consumption of dynamic power (CVDD2f) can be reduced as the operating voltage decreases. The current generated when the transistor is not operating is called the leakage current (IOFF). The static power (VDDIOFF) caused by leakage current can also reduce consumption as the operating voltage decreases. As such, as technology nodes advance, chip operating voltages will have to shrink with them (Figure 3). However, following traditional scaling methods, the scaling of operating voltages too have leveled off, remaining at 0.75V. Therefore, the adoption of new technologies that can continue to promote the reduction of operating voltage is a top priority for achieving lower power consumption. From the current formula 
, it can be seen that, under a fixed ION, if the 
increases, high mobility channels (
), high-κ gate dielectric (Cox) layers, and highly stacked channels (n) can decrease the , thus effectively scaling down the VDD and reducing the power consumption of the transistor (CVDD2f, where C is the capacitor and f is the frequency. Additionally, under a fixed ION, the ION/IOFF ratio can be increase via an ultrathin body, decreasing IOFF and causing the static power (VDDIOFF) to decrease.
 Figure 3: Operating Voltage (VDD), Gate Length (Lg) and Technology Node Relationship Diagram |
Starting from the 2nm technology node, the architecture of transistors changed from the FinFET transistor to the Gate-All-Around (GAA) stacked nanosheets transistor. GAA transistors have better gate control capabilities than FinFET transistors, which can effectively increase channel control capabilities and maintain the suppression of short channel effects. According to IMEC’s component blueprint (Figure 4) [2], GAA transistors will continue to be used in four technology nodes (N2, A14, A10, A7) and proceed to make use of complimentary field-effect transistors (CFET) at the A5 technology node. The main goal of size reduction and the continued advancement of Moore’s Law can be achieved through the vertical stacking of transistors. At the A2 technology node, atomic channels will be integrated into complimentary stacked transistors. In order to make stacked nanosheets sustainable, present research is focused on advanced nanosheet extensions that can integrate new technologies. These include high carrier mobility channels, high-layer stacked channels, and high k gate dielectric layers. TSMC demonstrated high mobility channel FinFET transistors at the 2019 IEDM and applied them in the 5nm technology node [3]. The channel material was silicon germanium (SiGe) [4]. Compared to silicon channel components, these provided higher transistor drive currents at the same leakage current. In terms of channel stacking, the Intel 20A technology node uses four-layer stacked channel nanoribbons (channel shape similar to that of nanosheets) [5]. TSMC demonstrated three-layer stacked channel nanosheets as a transistor structure for the 2nm technology node at the 2021 ISSCC [6]. CEA-Leti demonstrated seven-layer stacked silicon channel nanosheets at the 2020 VLSI [7]. This research team demonstrated eight-layer stacked Ge0.75Si0.25 nanosheets and seven-layer stacked Ge0.95Si¬0.05 nanowires at the 2021 VLSI [8]. Our work was selected as the 2021 VLSI Highlight Paper and published by the top international journal Nature Electronics Research Highlight [9].
 Figure 4: Blueprint of IMEC’s Transistor Structure [2] |
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In order to provide a greater transistor drive current within the same footprint, this research team continued to increase the number of channels stacked. By optimizing multi-layer germanium silicon epilayers and selecting the appropriate isotropic wet etching process, we successfully prepared 16-layer Ge0.95Si¬0.05 nanowires (Figure 5 Left). This transistor has a record high drive current (at VOV=VDS=0.5V, achieving 9400μA/μm per footprint). In order to further improve the transistor performance, a two-step wet etching process was used to successfuly prepare 12-layer Ge0.95Si¬0.05 nanowires without parasitic channels (Figure 5 Right). This transistor effectively reduced both sub-threshold swing (SS) and leakage currents. These research findings were published in the Nature/Communications Engineering [10]. At present, National Taiwan University is the only institution outside the industry which has long had the ability to develop multi-layer stacked channel transistors. It has become an important bridge between academia and the industry. |
 Figure 5: This research team published (Left) 16-layer Stacked Ge0.95Si0.05 Nanowires; (Right) 12-Layer Stacked Ge0.95Si0.05 Nanowires without Parasitic Channels [10] |
In addition to increasing the number of stacked channel layers, increasing the dielectric coefficient of the dielectric layer in the gate stack can also effectively increase the drive current of a transistor. This simultaneously reduces the difficulty of the manufacturing process by reducing the number of stacked channels. Using plasma-assisted atomic layer deposition (PEALD) to optimize Hf and Zr concentrations, HfxZryO2 dielectric layers can achieve a high dielectric coefficient. This research team successfully integrated Hf0.2Zr0.8O2 high dielectric coefficient (κ=47) dielectric layers into 8-layer stacked Ge0.95Si0.05 nanowires (Figure 6 Left) and nanosheets (Figure 6 Right). These research findings were published in the 2023 VLSI [11]. When VOV=VDS=0.5V, the nanowires and nanosheets have drive currents of 9200μA/μm per footprint and 360μA per stack respectively (the nanosheets have a record high drive current). In addition, it was confirmed through simulations that HZOcan has a peak dielectric coefficient at [Zr]=80%. Simulations also verified that high dielectric coefficient gate stacking combined with high-layer stacked channels can effectively reduce gate delay.
 Figure 6: This research team published the integration of the Hf0.2Zr0.8O2 high k dielectric layer with (Left) 8-layer Stacked Ge0.95Si¬0.05 nanowires and (Right) 8-Layer Stacked Ge0.95Si¬0.05 nanosheets [11]. ©2023 JSAP |
Germanium-based materials such as germanium silicon (GeSi), germanium (Ge) and germanium tin (GeSn) have better carrier mobility than silicon, enabling them to increase the drive current of transistors. They are also compatible with the current silicon semiconductor process technology in the industry, giving them the potential to become the next generation channel material. Research on the use of other novel, non-silicon-based materials, such as Oxide Semiconductors and 2D materials, as transistor channels has also been very prevalent in recent years. Among these materials, 2D materials, with their characteristic of being only a single layer of atoms, are considered to have great potential for miniaturization. Papers on related discussions can be found in Nature, IEDM and VLSI. However, 2D materials face technical challenges when it comes to growth on large area, high quality wafers as well as problems such as high contact resistance and low currents. It is also difficult for 2D materials to be compatible with the mature, silicon-based materials in the device manufacturing process. As such, there is a gap in device performance when compared to Group IV material transistors. When it comes to n-type transistors, most oxide semiconductors and 2D material transistors exhibit negative threshold voltages (VT) and very high overdrive voltages (VOV) (Figure 7 Top) [12], so they cannot be applied to our current advanced ICs. As for p-type transistors, most oxide semiconductors and 2D material transistors exhibit a very high VOV, which is also difficult to apply to advanced ICs (Figure 7 Bottom). In contrast, high carrier mobility Group IV materials can have higher drive currents even under low VOV conditions.
 Figure 7: Current and VOV Comparison Chart of Group IV Materials, Oxide Semiconductors and 2D materials in (Top) n-Type Transistors [12] © IEEE and (Bottom) p-Type Transistors |
According to IMEC’s component blueprint (Figure 4) [2], complimentary field-effect transistors (CFET) will be introduced with the A5 technology node (2032). Complimentary field-effect transistors can reduce the footprint of the inverter unit by up to half of what it is when using horizontally-placed transistors (Figure 8) [4]. This would enable an increase in the number of transistors per unit area, increase computing performance and continue to advance technology nodes. Thus, it has become an important topic of research. The industry is also actively developing complimentary field-effect transistors in preparation for the arrival of the transistor architecture that will succeed stacked nanosheets. At the 2023 IEDM, Intel (Figure 9 Top Left) [13], Samsung (Figure 9 Top Right) [14] and TSMC (Figure 9 Bottom) [15] all presented the results of their research and development of CFETs.
 Figure 8: Schematic Diagram of How Complimentary Field-Effect Transistors Reduce the Inverter Unit Footprint (Can Reduce to Up to Half the Original Area) [4]
Figure 9 (Top Left) Intel’s Complimentary Stacked Transistor [13] © IEEE; (Top Right) Samsung’s Complimentary Stacked Transistor [14] © IEEE; (Bottom) TSMC’s Complimentary Stacked Transistor [15] © IEEE |
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This research team has successfully developed a CFET structure for use in the 0.5nm (5Å) generation. The n-type and p-type nanosheet transistors were stacked vertically (Figure 10) to form an inverter structure, and inverter characteristics were measured successfully. Furthermore, the 3D monolithic stacking approach enables epitaxial growth of the channel layer of the underlying transistor, the sacrificial layer in the middle and the channel layer of the upper transistor. This process does not require wafer bonding, so it reduces both the process complexity and costs. High mobility germanium silicon channels are used as n-type and p-type nanosheets in complimentary field-effect transistors to improve performance. In the CFET structure, good isolation between transistors is needed to ensure that each transistor can operate independently without affecting one another. We used multi-layer P/N junctions for electrical isolation between stacked transistors. This approach does not require a complicated S/D regrowth process and can replace insulating layer deposition to effectively simplify the device manufacturing process. Relevant findings were presented at the 2022 IEDM symposium [16]. |
 Figure 10: The germanium silicon channel complimentary field-effect transistor published by this research team vertically stacks p-type nanosheet transistors on n-type nanosheet transistors to form an inverter unit [16]. © IEEE |
Using our prior experience in developing single chip CFET structures, this research team further optimized the process and achieved the world’s first single chip CFET integrating heterogeneous germanium tin and germanium silicon nanosheets (Figure 11). By growing the channel layer of the bottom germanium silicon nanosheet transistor, the middle sacrificial layer, and the channel layer of the upper germanium tin nanosheet transistor via epitaxy, the process does not need to use wafer bonding to achieve heterogeneous germanium tin and germanium silicon channel integration. Furthermore, by using the band alignment between germanium tin and germanium silicon channels, it is possible to achieve a VT matched inverter using only a single metal work function gate stack (Figure 12), eliminating any need for the complex high aspect ratio, bimetal work function gate stacking process. Heterogeneous GeSi and GeSn channel complimentary field-effect transistors can have better inverter characteristics than VT mismatched GeSi CFETs. In addition, the integration of a high dielectric constant Hf0.2Zr0.8O2 gate dielectric layer can effectively improve the performance of the complimentary field-effect transistor. Relevant findings were presented at the 2023 IEDM symposium [17].
 Figure 11: The heterogeneous germanium tin and germanium silicon channel CFET published by this research team successfully stacked p-type germanium tin nanosheets vertically on h-type germanium silicon nanosheets to form an inverter unit [17]. © IEEE
Figure 12: A VT matched inverter can be achieved using the band alignment between heterogeneous germanium tin and germanium silicon channels [17]. © IEEE |
In lieu of the current status of research and development, a lot of work is still needed if 2D materials are to replace silicon-based materials in mainstream technology.
Reference:
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[12] W.-J. Chen et al., “Extremely High-κ Hf0.2Zr0.8O2 Gate Stacks Integrated Into Eight Stacked Ge0.95Si0.05 Nanowires and Nanosheets nFETs to Boost ION,” IEEE Transactions on Electron Devices, 70, 12, 2023.
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[14] J. Park et al., “First demonstration of 3-dimensional stacked FET with top/bottom source-drain isolation and stacked n/p metal gate,” IEEE International Electron Devices Meeting (IEDM), 29-4, 2023.
[15] S. Liao et al., “Complementary Field-Effect Transistor (CFET) Demonstration at 48nm Gate Pitch for Future Logic Technology Scaling,” IEEE International Electron Devices Meeting (IEDM), 29-6, 2023.
[16] C.-T. Tu et al., “First Demonstration of Monolithic 3D Self-aligned GeSi Channel and Common Gate Complementary FETs by CVD Epitaxy Using Multiple P/N Junction Isolation,” IEEE International Electron Devices Meeting (IEDM), pp.479-482, 2022.
[17] C.-T. Tu et al., “First Demonstration of Monolithic Self-aligned Heterogeneous Nanosheet Channel Complementary FETs with Matched VT by Band Alignments of Individual Channels,” IEEE International Electron Devices Meeting (IEDM), 29-5, 2023.
