Decrypt Advanced Process Failure Analysis! Master the Key Technologies

Advanced manufacturing processes have always played a pioneering role in IC development trends. These developments have relied heavily on the unique R&D capabilities of Taiwan’s TSMC to sustain Moore’s Law. In addition to the reduction of component sizes, the characteristics of advanced manufacturing processes include packing more transistors into the same area and having faster response times, so ICs using these advanced processes are all used in products that require large numbers of calculations. Such products include mobile phone processors, graphics processors, data center servers and mining machines. An examination of the product division of TSMC makes it clear that such ICs play a decisive role in TSMC’s revenue.

Figure 1 shows the proportions of TSMC’s 5 main product types in 2021. Among them, High Performance Computing (HPC) not only accounted for 37% of revenue but also had a growth rate as high as 34%. Both its current scale and future growth have a lot of weight. It also shows that there is considerable demand for failure analysis.

Figure 1. Revenue Proportion and Growth Rate of Various TSMC Product Types in 2021

Advanced process ICs also have several other structural and material characteristics, such as a complexity of circuit design, larger die sizes, advanced packaging, three-dimensional FinFET components, and special metal and dielectric materials, etc. Compared with traditional process designs, these characteristics further increase the difficulty of failure analysis. With the advent of new analysis instruments and the development of new analysis techniques, however, MA-tek has made great progress in advanced process analysis. Below are introductions to some of these key analysis technologies.

A Solid Immersion Lens (SIL) is a solid, hemispherical piece of material with a high refractive index that is fixed in front of a lens. It needs to be attached to the sample when shooting. Its purpose is to increase the Numerical Aperture (N.A.) to increase the light-gathering power of the lens, thereby improving the resolution to meet the precision positioning requirements of advanced processes. This, in turn, improves the success rate of subsequent defect detection.

Figure 2 illustrates the principles behind the SIL. It is clear from the spot size formula that, by expanding the light collection angle via the hemispherical SIL—in other words, by increasing the N.A value, lenses equipped with SIL have a smaller spot size and can operate at smaller sizes. Therefore, where the traditional objective lens can only reach a magnification of 100 times, the magnification of the SIL lens can be as high as 350 times. This immediately improves its analysis capabilities by 3.5 times that of the traditional positioning method. Figure 3 shows the superiority of this lens. It can clearly locate a single component even for 5nm products.

Figure 2. Schematic Diagram of the Principles Behind the SIL; in the Spot Size Formula, the n is the Refractive Index, the λ is the Wavelength, and the θ is the Angle of Incidence.

Figure 3. Comparison of Images Captured via Traditional and SIL Lenses（Reference：ThermoFisher Meridian Introduction）

1. Manual Grinding

Typically, in the integrated circuit failure analysis process, sample preparation is conducted via delayering after positioning. As processes get smaller, the inter-metal dielectric (IMD) layer is also getting thinner. Therefore, the removal of each layer tests the experience and care of personnel. Furthermore, the use of the TaN buffer layer and the low-k dielectric layer cause serious grinding differences, making the field of observation extremely narrow. Fortunately, thanks to the efforts of the MA-tek R&D team, a special chemical formula has been developed that can solve this layer difference problem, expanding the observation range by hundreds of um. Like the recipe for Coca-Cola, this incredible secret is locked away far from prying eyes.

2. Automated Grinding

IC backside thinning is a commonly used method in bright spot positioning. In particular, the metal layer of advanced processes can consist of more than ten layers, making it difficult to measure bright spots from the front side of the chip. In addition, packaging methods for these processes often adopt the flip-chip architecture. What’s more, the luminous efficiency of advanced processes is not as good as that of traditional processes. So, IC back highlights are used very frequently. Naturally, IC backside thinning has become a necessary sample preparation method for advanced manufacturing processes. However, when the IC back thickness is below 100um, this can result in chip warpage. The stress of grinding can then easily cause die cracking problems.

MA-tek’s current automated grinding machine can adjust automatically to the degree of chip warpage, thus reducing the risk of preparation failure and increasing the flatness of the grind. More importantly, this automated grinding machine has the ability to measure thickness. As such, the thickness can be precisely controlled within a range of 1um. The SIL lens mentioned above has requirements in regards to the thickness of chips, so SIL lenses and this automated grinder are a perfect combination. In the future, when it becomes necessary to use IC back visible light positioning technology, chips will have to be as thin as 5um. At that point, automated grinding machines will be essential. In addition to its uses in IC backside grinding, it can also be used in chip-fronts and package structures, as well as a wide range of other applications.

Figure 4. Automated Grinding of Various Types of Products（Reference：X-prep Product Information Guide）

3. P-FIB delayer

In terms of IC delayering, in addition to manual grinding, there is the P-FIB delayering option. P-FIB is a form of large-scale planer etching using xenon ions. It can operate on an area of up to 200um x 200um in addition to meeting flatness requirements. Most importantly, however, it can reduce the carbon deposition phenomenon.

Carbon deposition can occur after samples are treated with chemicals and abrasives during processing or if samples are inadvertently exposed to microscopic bits of contamination. These non-sample foreign objects are composed mainly of hydrocarbons. Some will remain on the wafer even after cleaning. Under electron beam irradiation via SEM, the carbon-hydrogen bonds are broken, resulting in carbon sputter contamination on the sample. It goes without saying that this unintended sputtered layer affects the subsequent processes. It will also affect the contact of the nano-probe which will be discussed later. Therefore, if nano-probing is to be performed during the advanced process, P-FIB delayering is an absolutely essential step.

In order to screen out problems during testing, digital circuits often include a DFT (design for test). This test helps uncover possible failure paths, also known as scan paths. Defects can occur anywhere along that path. The path transmits signals through the interconnect, or metal / via wiring. Traditionally, layer-by-layer removal is used to locate defects using layer-by-layer observation. As you can imagine, as the observation areas increase and wire diameters shrink, the success rate of this method drastically decreases.

The most effective way to successfully identify the exact locations of defects is to locate bright spots during dynamic testing. The most common methods are LVP (laser voltage probing) and TRE (time-resolved emission), but these kinds of verification are too expensive for most companies. They are not economical approaches. Since EBAC can show the winding path of the interconnect, it has the potential to find the defect in the winding path and determine the root cause of a ‘scan fail’. Therefore, if the problematic signal can be found first through testing, one can then use EBAC to pinpoint the spot on the metal line that corresponds to that signal. Finding possible defect locations is a powerful tool for the failure analysis on digital circuits, especially in more advanced processes.

Figure 6. EBAC Can Display the Maze-Like Metal Interconnect Connected to Pinpointed Locations

EBIRCH stands for Electron Beam Induced Resistance Change. The difference between it and OBIRCH is that its excitation source is an electron beam as opposed to infrared light. Otherwise, the principle is the same. From this, it can be understood that Its resolution is better than that of OBIRCH because it uses an electron beam as its excitation source. OBIRCH involves placing a needle on the die PAD to locate the defect in the chip. This is done before the location of the defect is known.

To use EBIRCH, the problematic signal line needs to be identified in advance. Only then can the needle be placed on the corresponding metal line or via/contact. Under this premise, the precise defect location can be identified and assessed in combination with the layout. You can then proceed with further sample preparation and physical property observation.

Figure 7. After confirming the gate short to source via nano-probe, the defect was successfully located using EBIRCH.

Sometimes the defect cannot be found even after delayering to the bottom layer and continuing seems futile. Have you wasted a sample for nothing? Don’t despair just yet. This is when you should use a nano-probe to directly measure the electrical behavior of the component. Once the leakage path is confirmed, the subsequent PFA steps can be planned easily.

The nano-probe is also an indispensable tool in SRAM cell measurement. Although plan-view TEM is a quick way to find defects, after analyzing nearly a hundred FinFET SRAMs, MA-tek has found that there are many cases where the P-V TEM is insufficient. In these cases, the locations of the abnormalities can be determined using the electrical measurement of a nano-probe. You can then make the correct choice in terms of section position.

There are two types of nano-probes: AFM-based and SEM-based. After many years of performing AFM-based nano-probing, MA-tek has accumulated a wealth of experience and built up an extensive “nano-probing + PFA” analysis database. At present, our success rate with analyzing 12nm FinFETs is almost a hundred percent. The advantage of using an AFM-based nano-probe is that it has high operating efficiency. There is no problem with electrical drifts caused by charge accumulation. As such, it is still the machine of choice for most companies.

As processes evolve and shrink to below 7nm, however, the AFM-based nano-probe is reaching its limits. This is where the SEM-based nano-probe comes in handy! At present, MA-tek is collaborating with various international manufacturers on the measurement and analysis of 5nm products, laying a solid foundation for other manufacturers looking to enter the 7nm/5nm process field.

Figure 8. Measurement of 12nm FinFET SRAM

Figure 9.　Measurement of 7nm FinFET SRAM

Due to the tiny size of FinFET components, it is not possible to use FIB to find defects while cutting even if the location of the defect is confirmed. On one hand, there is the problem of resolution. On the other hand, the defect may also be too small and thus would be missed. Therefore, the high-resolution TEM is a more suitable observation tool.

The TEM observation method is divided into two steps. The first step is to use P-V TEM to observe a large area and confirm the defect location. The second is to use X-S TEM on specific, suspected defects. Although it requires two processes, it greatly improves the success rate of analysis. This two-step TEM observation method both observes the planer surface and inspects the cross-section. Therefore, it is known as 3D TEM, and it is widely used in the FinFET structure observation. It is the final key piece of total-solution for FA.