3D IC Packaging: Ultra High Density Copper-Copper Heterogeneous Integration

It is no longer possible to meet the needs of the semiconductor industry by merely continuing down the Moore's Law IC technology development route. Research has shown that the growth of the volume of global data computing over the past 10 years has exceeded that of the past 40 years combined. Many emerging applications and technologies, such as AI artificial intelligence, 5G communication, the Internet of Vehicles, Metaverse, and industry 4.0, all require fast, timely processing of massive amounts of data. This has led to the development of two major, related fields: mobile computing and high performance computing (HPC). These fields have become the most important drivers of growth in the global semiconductor market.

In fact, as computing demand grows exponentially, even shrinking transistor sizes to the absolute limit to improve performance falls short of meeting the needs of future industrial applications. To break through this bottleneck, in addition to continuing to develop advanced processes and striving to reach the target 2nm line width, the semiconductor industry is simultaneously searching for other solutions that can keep chips small in size while maintaining the high efficiency of emerging technologies. To this end, in recent years, researchers have begun to look for new solutions in packaging technology. The three-dimensional architecture layout can greatly improve the intuitiveness of contact interconnection concepts. It has led to the evolution from the 2D plane to the 3D stack and the move from single chips to the multi-chip “Heterogeneous Integration Design Architecture System (HIDAS)” advanced packaging technology route of development.

According to various market research institutions, from 2020 to 2026, the advanced packaging market’s compound annual growth rate (CAGR) will be as high as 8%. By 2025, the market revenue is expected to exceed 42 billion USD. In order to achieve technological leadership in the semiconductor field, well-known manufacturers such as TSMC, Samsung, Intel, Infineon, Freescale, and ASE have increased their investments in related R&D and capacity expansion. They have also developed and launched their own innovative packaging technology solutions in the hopes of becoming a cornerstone of the future era of semiconductor hegemony.

In terms of the overall evolution of technology, the use of 2.5D/3D packaging architecture has become an inevitable development trend. As for how to improve the density of chip contact interconnection, the extreme heterogeneous integration of various Chiplets is expected to become the core technology advantage in the field of advanced packaging. In truth, Gordon Moore stated in his thesis as early as 1965 that “It has been shown that it is more economical to build large systems using smaller functional modules (packaged and interconnected individually)”. Adopting the 2.5D/3D three-dimensional packaging design to stack and integrate different electronic components in a single chip can enable us to overcome space constraints, effectively improve power consumption and performance, and greatly reduce chip sizes.

However, the technical advantage of this multi-dimensional packaging architecture is, in essence, the increase of contact density. Under the premise of maintaining the same computing performance, improving the contact density of chip interconnection would enable us to further reduce the number of layers in the stack, thus reducing power consumption and packaging costs. Therefore, it is clear that interconnection technology with an ultra high I/O count will be the key to victory in the field of advanced packaging in the future.

In this issue of the “New Technology Channel | Collaboration Column”, MA-tek has specially invited Professor Zhi Chen, a top scholar in the field of semiconductor materials, to provide us with a comprehensive overview of the development of copper-copper contact interconnection process technology for advanced packaging applications. The copper process is a very mature technology in the semiconductor field. In metal interconnect architecture using copper-copper bonding, the contact pitch can be scaled down to less than 1 micron. Therefore, more than 1 million contacts can be made within a chip area of 1cm2. This offers an excellent opportunity to achieve extreme heterogeneous integration beyond the limitations of Moore's Law. We hope that this article will help our readers understand the progress being made in the academic research in this important scientific and technological field.

Director of R&D Center & Marketing Division, Chris Chen, 2022/07/20

3D IC Packaging: Ultra High Density Copper-Copper Heterogeneous Integration

Professor Chih Chen

Ph.D. students：Hung-Che Liu

Department of Materials Science and Engineering, National Yang Ming Chiao Tong University

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Moore's Law predicted that the number of transistors per unit area inside a chip would double every 18 months. This forecast predicted that 5nm node mass production would be reached by 2020, after which it would become necessary to develop a mass production process for the 3nm node. However, production costs have increased significantly. Some experts therefore predict that, in the future, Moore’s Law will either be hampered by physical limitations or by cost considerations.

Many researchers have proposed a variety of new solutions that leverage other techniques to improve chip performance in what will come to be known as the “Post-Moore Era”. The solutions that have garnered the most attention are Heterogeneous Integration and Chiplet technology. Heterogeneous Integration integrates different functional chips using 2.5D/3D packaging technology to get a multi-functional chip. Chiplet technology improves performance by splitting the same function or splitting a large chip into small chips then using packaging technology to integrate them together. Figure 1 ranks the different packaging technologies experts expect to use to improve chip performance [1]. The key to both these solutions is Advanced Packaging technology. Therefore, experts and manufactures alike need to invest their efforts into 2.5D and 3D packaging technology.

Figure 1.  Advanced Packaging Rankings for Die Performance and Contact Density [1]

The earliest form of packaging technology was the Wirebond. Because its contacts can only be arranged on the periphery around the chip, there is no effective way to increase the number of I/O contacts. So IBM proposed Flip Chip bonding, which used a Solder Bump as a contact to bond two chips. Contacts are arranged in an array and can be distributed over the entire chip, and shrinking the size of the solder bump is an effective way to increase the number of I/O contacts.

The Flip Chip solder bonding process is shown in Figure 2. The bonding process takes advantage of the low melting points of lead-free solder and copper, which makes the contacts stabilize at about 230℃. The gaps between contacts are then filled with Underfill. This improves the contacts’ mechanical properties. When the contact pitch is reduced to about 10 microns, however, many problems start to arise, e.g. the smaller the contact, the smaller the solder ball, which makes it easy for the solder ball to fully react and form Intermetallic Compound (IMC) contacts. The mechanical properties and electrical conductivity values of IMC contacts are greatly reduced. If the contact pitch is too small, adjacent solder balls can easily end up touching during the Reflow Process, resulting in chip failures caused by Bridging issues. Also, the smaller the distance, the more difficult it becomes to fill in the Underfill. Even though it can be scaled down, the resistivity of solder and IMC is about 10 times that of copper. Therefore, they are also unsuitable for high performance component packaging.

Figure 2. Flip Chip Bonding Flowchart (a) Un-bonded Test Piece, (b) Joint After Reflow, (c) Underfill Filling Process, (d) Contact Diagram After Filling. [1]

Therefore, some scholars have proposed using Cu-Cu Hybrid Bonding technology, which inlays metal contacts between Dielectric Materials and uses heat treatment to join two materials at the same time. Bonding is achieved via the atomic diffusion of copper metal in the solid state, so there are no Bridging problems. The copper process is a very mature technology in the semiconductor industry. Copper-to-copper contact pitch can be scaled down to less than 1 micron, so it is possible to make over 1 million contacts within a 1x1cm² wafer. As such, the direct bonding of metals becomes very important. Figure 3 shows the number of contacts that various packaging technologies can achieve in a 1x1cm² chip [2].

Heterogeneous Integration has three advantages over Flip Chip technology. The first is the ability to achieve ultra fine pitch and ultra small contacts. This means it can achieve a very high number of I/Os. Second, the replacement of Underfill with dielectric material bonding can save filling costs. Third, in Flip Chip technology, solder balls result in a thickness of about 10 to 30 microns between the wafer and the substrate. In contrast, heterogeneous bonding has almost no thickness. Future developments in 3D packaging will require the stacking of numerous layers of die. Therefore, the overall thickness could be greatly reduced by using heterogeneous bonding. The first to realize Direct Bond Interconnection (DBI) was Ziptronix (now Xperi) [3]. The steps for bonding are shown in Figure 4.

First, prepare the wafer with silicon dioxide, the dielectric material, and copper contact metal. At this point, the thickness of the copper portion will be slightly less than that of the dielectric material. Perform surface activation treatment using Plasma and align the wafers face to face at room temperature. Due to the Van der Waals force, it will have a certain level of bond strength. Then the condensation reaction between SiO2 and SiO2 is carried out by maintaining the temperature at 100℃. This forms strong covalent bonds to improve the bond strength. Then raise the temperature to between 300℃ and 400℃. At this time, because the thermal expansion coefficient of copper is greater than that of SiO2, the copper surfaces will come together and be naturally subjected to a compressive stress, facilitating the diffusion bonding of copper contacts.

Figure 4. Heterogeneous Bonding Flowchart (a) Un-bonded Specimen, (b) Dielectric Material Bonding Step, (c) Elevated Temperature Copper Contact Bonding Process, (d) Stress Distribution Inside the Contact Under High Temperatures. [3]

According to researchers, the difference in height between the dielectric material layer and the metal layer after chemical polishing is the key to achieving low temperature bonding. The choice of grinding fluid and parameters is the main reason for different thicknesses. With a smaller difference in thickness, the copper surface can be brought into contact at a lower temperature, and the bonding can begin.

In 2016, Sony was the first to apply heterogeneous integration technology in the Backside-illuminated CMOS Image Sensor (BI-CIS) of its Samsung Galaxy S7, greatly improving the resolution of its camera lens. Figure 5 shows its cross section [4,5]. TSMC applied this technology to its System on Integrated Chip (SoIC). Figure 6 is a schematic diagram showing the current development of TSMC’s SoIC [6,7]. In Figure (b), it can be seen that the Insertion Loss performance of heterogeneous integration is significantly better than that of traditional Flip Chip soldering, and the number of contacts can be increased from 10 times to more than 1,000 times. TSMC’s Zhunan plant will also be fully investing itself in 3D-IC Heterogeneous Integration.

Figure 5. Cross Section of the Sony Samsung Galaxy S7 BI-CIS Lens Utilizing Heterogeneous Bonding [4,5]

Figure 6. Schematic Diagram of TSMC’s System on Integrated Chip (SoIC) [6,7]

Figure 7 shows the results of Intel’s Heterogeneous Integration research [8]. Compared to Flip Chip bonding technology, the number of contacts per square nanometer increases from 400 to 10,000. In the future, when the gap is reduced to 1 micron, the number of contacts could go all the way up to a million. At the end of 2021, AMD announced that it has already adopted TSMC’s Cu/Oxide Hybrid Bonding high density packaging technology in its Server Processor. Early in 2022, they also announced that the Processor in their high end laptops, the Ryzen 7 5800X3D, also makes use of Hybrid Bonding technology, stacking a 7nm SRAM on a 7nm Processor. In contrast to solder Microbumps, using Cu Hybrid Bonding can increase the contact density by 200 times while reducing the energy required for each signal transmission to less than one third.

Figure 7. Cross Section Comparison of Intel’s Heterogeneous Bonding and Microbump Contacts [8]

As such, Hybrid Bonding technology has gradually drawn the attention of international manufacturers and has even been included in the Roadmap. In fact, there are many manufacturers in addition to those mentioned above, such as IMEC, GlobalFoundries, and Leti, who have invested in this research. Its importance cannot be overemphasized.

Currently, if Heterogeneous Integration is to be used in mass production, it is necessary to perform wafer to wafer (W2W) bonding before then cutting into small pieces. However, using W2W would mean that the upper and lower wafers are limited to being the same size. Otherwise, there will be areas wasted. In recent years, some scholars have been working to further reduce the bonding temperature and time through various methods as optimized bonding conditions would facilitate Chip to Wafer (C2W) and Chip to Chip (C2C) mass production. At this stage, the research on using SiO₂ as the dielectric material is the most mature. It enables low temperature bonding with the help of Plasma. Scholars are also studying other types of dielectric materials, such as SiCN and various polymers. Various scholars have also conducted extensive research on the bonding mechanism of copper contacts and how to reduce their bonding temperatures.

Copper’s biggest advantage is that it is cheaper than other metal materials. It also has good electrical conductivity, thermal conductivity and anti-electromigration properties. As such, it will certainly be an important contact material in the future. However, copper oxidizes easily at high temperatures, and having copper oxide on the surface is very unfavorable to the formation of stable contacts. At present, copper generally requires surface activation in a suitable vacuum environment of between 300℃ and 400℃ or in an ultra-high vacuum to be firmly bonded. Research on fast copper-to-copper direct bonding is essential for mass production.

At present, the best method for creating copper contacts is Thermal Compression Bonding. To achieve low temperature bonding, scholars have developed the following methods. The first is to coat the surface of the copper contacts with a Passivation Layer before joining, this preventing copper oxide formation to achieve low temperature bonding. Commonly used passivation metals include silver [9], gold [10] and platinum [11], etc. Another method to facilitate low temperature bonding is to improve the bonding surface diffusion coefficient.

In 2012, our research team discovered that nano-twin crystal copper can be prepared via DC electroplating [12]. Analysis conducted with our advanced instruments revealed that the surface has the preferred orientation (111). In 2014, it was reported that bonding can be completed in 60 minutes with the preferred surface (111) at 150℃ [13]. Further research found that using copper with the highly preferred (111) surface can greatly increase the diffusion coefficient of the surface, enabling the elimination of interface voids at low temperatures or in short times to form stable copper contacts. Furthermore, it was found through oxidation experiments that when the surface orientation is (111), the surface oxide will be less than it is for other crystal planes [14]. The reason for this is that, in the face-centered cubic stacking structure, the (111) grain surface has the least bond breakage, making it less likely to form oxides.

In 2019, the further preparation of nano-twin structures into copper bumps showed that, at 300℃ and 90MPa, it only takes 10 seconds to complete bonding and obtain a reliable contact strength [15]. This is called Instant Bonding. Although the temperature is still a little high, the ability of these bonding conditions to enable the completion of wafer pre-bonding in just 10 seconds will be very helpful to future C2W and C2C bonding by significantly reducing bonding costs. In 2021, our research team also successfully completed the heterogeneous bonding of nano-twin crystal copper/SiO₂ [16]. The bonding can be completed with the temperature maintained at 200 ℃.

Our research team has divided Thermal Compression Bonding into the following four stages. Each stage is distinguished by the changes in the voids and microstructure of the copper contacts. Figure 8 is a flowchart of the four stages. 

Figure 8. Flowchart of Bonding Stages

The first stage is centered on “Plastic Deformation”. Initially, the surface of the copper contact is extremely bumpy and uneven. Since the contact area is small, the downward force applied can easily exceed the Yield Strength of the metal. This leads to plastic deformation, which reduces the gaps between the contacts for a short period of time. At this time, the contact areas should be in a state between a grain boundary and a surface. We call this a Quasi Grain Boundary. The areas that don’t touch will form irregularly shaped voids.

The second stage is centered on “Creeping”. The coupling ratio decreases as plastic deformation occurs, and the compressive stress will drop below the Yield Strength. Although it is lower than the Yield Strength at this time, the material is still under a downward pressure, resulting in a Stress Gradient at joints and voids. This Stress Gradient will diffuse the copper atoms and continue to shrink the voids. The surface copper atoms and opposite copper atoms will start to form metallic bonds, and the quasi grain boundary will begin slowly transforming into an Interfacial Grain Boundary. In 2021, our team built a diffusion model and calculated the bonding time (t_bonding) as shown in equation 1 [17]. Equation 1 can help us determine the relationship between the bonding time, surface roughness (Rq), bonding temperature, downward pressure and effective diffusion coefficient (D_eff).

Since the bonding mechanism is dominated by surface diffusion in the initial stage then by grain boundary diffusion in the later stage, the value of the effective diffusion coefficient will be between the surface diffusion coefficient and the grain boundary diffusion coefficient. In addition, as the engagement ratio becomes larger and larger or transforms into grain boundary diffusion, the creep deformation rate will be greatly reduced. After this stage, there will be voids of different sizes left in the interface.

Next, we enter stage three, “Void Ripening”. In this stage, we start to see larger voids grow and smaller voids shrink. This is because, at this stage, the voids are working to reduce the overall energy. Small voids have greater Gibbs free energy and are less stable. As such, the small voids will move towards the large voids along the interfacial grain boundary. This leads to void ripening, which makes the average void size larger [18].

The last stage is the “Interface Elimination” stage, where interfacial grain boundaries are eliminated by grain growth. Voids are left inside the grain. The path of void diffusion will be changed from grain boundary diffusion to Lattice Diffusion, resulting in a significant decrease in the void diffusion rate. At this point, void sizes can be difficult to change. In other words, the average void size will change very little.

Analysis of the joints after bonding is very important. One common nondestructive analysis method is to use a Scanning Acoustic Microscope (SAM) to confirm whether the bonding was successful. This is done by checking the joint test piece for gaps using ultrasonic penetration. If there is a gap, it is a joint failure area. These can be further observed with an ultra high resolution 3D X-Ray microscope. The image resolution of the two analysis methods above can only reach the tens of microns to 1 micron. However, preliminary observations using destructive analysis (FIB) can confirm that there are small voids of tens of nanometers in size in the actual bonding interface. If we use purely nondestructive analysis, it is difficult to observe all the interface voids. Therefore, most of the current methods for detecting voids in joints use destructive analysis. However, this method of electron microscope image analysis of the cross section of the joint still has its shortcomings. The number of interface voids it can observe is very limited, so it is unable to realistically render the porosity of the joint.

Our team and MA-tek have jointly developed new copper contact interface observation methods. One is the preparation method using TEM thin slices shown in Figure 9. We refer to this as the Plan-view Type. This method starts by completely excavating the joint interface, so the entire thin slice is the bonding interface. Then the top view of the bonding interface is observed and photographed using an electron microscope, and the statistical information on the number and size of interface voids is collected. The image example in Figure 10 is the actual result of the Plan-view Type analysis of an interface. Compared to the general Cross-sectional Type approach, the Plan-view Type can not only observe the top view of the interface but also observe a larger number of voids within a small area. Additionally, the range of void sizes that can be analyzed is also greater at approximately between 10 and 100 nanometers. This is very helpful for the study of voids.

Figure 9. Two Ways to Observe Voids in Copper Contacts via Transmission Electron Microscope Thin Slice Preparation

Figure 10. The Difference Between the Two TEM Preparation Methods Under the Same Conditions for Observing the Voids in a Copper Contact

The second method is to observe the voids using the FIB system in combination with a high resolution SEM. We call this Cut and View. The analysis method is shown in Figure 11. This method is more suitable for the analysis of samples with slightly larger voids in the bonding interface (at least 70nm). The SEM continues to shoot as the ion beam cuts, taking photos at short intervals. After making all the photos into overlays, the number and size of all voids can be confirmed. The two analysis methods discussed above will both be very important in the future. At present, the contact size for heterogeneous bonding can be less than 1 micron. Therefore, analysis of the contacts typically requires the help of an electron microscope, and the above analysis methods can effectively observe the internal voids of copper contacts.

Figure 11. Diagram of the Cut and view Analysis Method

Copper heterogeneous bonding technology enables ultra high packing density and provides excellent electrical and thermal conductivity. It is expected that it will soon be widely used in High Performance Computing. However, the process yield of this technology still needs to be improved. Also, there is still very little research on its structural reliability, such as its electromigration and thermal cycling. There is need for both the industry and academia to invest more resources in order to accelerate development.

Reference:

[1] Lau, J. H. (2022). Recent advances and trends in advanced packaging. IEEE Transactions on Components, Packaging and Manufacturing Technology, 12(2), 228-252.

[2] King-Ning Tu, Chih Chen, Hung-Ming Chen, Electronic Packaging Science and Engineering, Wiley,2021.

[3] Q. Tong, G. Fountain, and P. Enquist, “Method for low temperature bonding and bonded structure,” U.S. Patent 6 902 987, B1, Feb. 16, 2000.

[4] Y. Kagawa et al., “An advanced CuCu hybrid bonding for novel stacked CMOS image sensor,” in Proc. IEEE 2^nd Electron Devices Technol. Manuf. Conf. (EDTM), Mar. 2018, pp. 1–3.

[5] G. Gao et al., “Die to wafer stacking with low temperature hybrid bonding,” in Proc. IEEE 70th Electron. Compon. Technol. Conf. (ECTC), Jun. 2020, pp. 589–594.

[6] M. F. Chen et al., “SoIC for low-temperature, multi-layer 3D memory integration,” in Proc. IEEE 70th Electron. Compon. Technol. Conf. (ECTC), Jun. 2020, pp. 855–860.

[7] M.-F. Chen, F.-C. Chen, W.-C. Chiou, and D. C. H. Yu, “System on integrated chips (SoIC(TM) for 3D heterogeneous integration,” in Proc. IEEE 69th Electron. Compon. Technol. Conf. (ECTC), May 2019, pp. 594–599.

[8] R. Mahajan and S. Sane, “Advanced packaging technologies for heterogeneous integration,” in Proc. IEEE Hot Chip Conf., Aug. 2021, pp. 1–44.

[9] Chou, Tzu-Chieh, et al. "Electrical and reliability investigation of Cu-to-Cu bonding with silver passivation layer in 3-D integration." IEEE Transactions on Components, Packaging and Manufacturing Technology 11.1 (2020): 36-42.

[10] Wu, Yu-Ting, and Chih Chen. "Low temperature Cu-to-Cu bonding in non-vacuum atmosphere with thin gold capping on highly (111) oriented nanotwinned copper." Journal of Electronic Materials 49.1 (2020): 13-17.

[11] Liu, Demin, et al. "Investigation of low-temperature Cu–Cu direct bonding with Pt passivation layer in 3-D integration." IEEE Transactions on Components, Packaging and Manufacturing Technology 11.4 (2021): 573-578.

[12] Liu, Tao-Chi, et al. "Fabrication and characterization of (111)-oriented and nanotwinned Cu by DC electrodeposition." Crystal Growth & Design 12.10 (2012): 5012-5016.

[13] Liu, Chien-Min, et al. "Low-temperature direct copper-to-copper bonding enabled by creep on (111) surfaces of nanotwinned Cu." Scientific reports 5.1 (2015): 1-11.

[14] Tseng, Chih-Han, King-Ning Tu, and Chih Chen. "Comparison of oxidation in uni-directionally and randomly oriented Cu films for low temperature Cu-to-Cu direct bonding." Scientific reports 8.1 (2018): 1-7.

[15] Shie, Kai Cheng, Jing-Ye Juang, and Chih Chen. "Instant Cu-to-Cu direct bonding enabled by< 111>-oriented nanotwinned Cu bumps." Japanese Journal of Applied Physics 59.SB (2019): SBBA03.

[16] Ong, Jia-Juen, et al. "Low-Temperature Cu/SiO2 Hybrid Bonding with Low Contact Resistance Using (111)-Oriented Cu Surfaces." Materials 15.5 (2022): 1888.

[17] Shie, Kai-Cheng, et al. "A kinetic model of copper-to-copper direct bonding under thermal compression." Journal of Materials Research and Technology 15 (2021): 2332-2344.

[18] Liu, Hung-Che, et al. "Interfacial void ripening in CuCu joints." Materials Characterization 181 (2021): 111459.

The semiconductor packaging industry is currently undergoing a Paradigm Shift, where its technological evolution trend is shifting focus from the traditional PCB to the IC process. Many new types of advanced packaging architectures and design concepts, such as heterogeneous wafer integration, 3D wafer stacking (3D IC), fan out wafer level packaging (FOWLP), Chiplet modeular architecture and other innovative technologies, are developing rapidly. They are reinvigorating the growth of the global semiconductor market. In truth, many emerging industry applications, such as AI, 5G communication, autonomous driving, and the metaverse, etc., require high speed computing, low power, and low latency advanced chips for massive data processing. The original, traditional 2D packaging chip has limited functions due to the components that can be integrated. It has been unable to meet the requirements of these emerging market applications. As a result, chip manufacturers have turned to the packaging field in search of innovative solutions.

Currently, the two main axes of technological development in the field of advanced packaging that are recognized by the industry as having the greatest potential for realizing More than Moore are “Heterogeneous Integration (HIDAS)” using 2.5D/3D stereo stacking and the “Chiplet Module” architecture interconnected via Silicon Interposers. Heterogeneous Integration is, broadly speaking, the combination of two or more chips with different functions, such as memory and logic chips, optoelectronics and electronic components, or sensor and reading circuits, etc., integrated through the 2.5D/3D chip stacking packaging process. Heterogeneous integrated packaging has been regarded as the next major boost to the continued development of the semiconductor industry. It can make use of the inherent advantages of multi-dimensional space and multi-chip interconnection to achieve the high performance, small size, low power consumption and low cost package integration goals.

The basic concept of 2.5D packaging is to use a silicon interposer made of silicon wafers to connect several wafers with different functions, which are placed on the board side by side or stacked. After they are connected to form a specific functional module, one or several different functional modules are packaged with a PCB substrate. The silicon interposer typically has a through-silicon vias (TSV) structure, which can provide front and back contact signal connections with a fine pitch. The chip and silicon interposer, and the silicon interposer and the PCB substrate, are connected to each other by Micro Bumps and Solder Bumps respectively. Using the silicon interposer’s fine pitch connections to integrate functional modules, multiple chips with different functions can be packaged into a single chip with higher performance. It can realize tighter interconnections between the die and package substrates and improve package costs and size.

The well-known 2.5D packaging technology, the CoWoS (Chip On Wafer On Substrate), was developed by TSMC over many years. The package structure is a combination of multiple chips, such as processors or memory, which are first integrated on a silicon wafer with a silicon interposer structure through the CoW (Chip on Wafer) process. The wafer is then cut. Then the removed CoW wafer is connected to a substrate to further package it into a CoWoS chip. This packaging technology allows wafers to achieve small physical sizes, low power consumption, fewer pins and other advantages. In 2016, TSMC used this technology to defeat then competitor Samsung and win the Apple iPhone 7/7Plus’ A10 processor order and achieved stable mass production, showing its technical strength in the field of advanced packaging to the outside world for the first time.

Like the CoWoS, the FOWLP (Fan-Out Wafer Level Packaging) is also a mainstream 2.5D packaging technology. After years of research and development, well-known manufacturers including TSMC, Infineon, Freescale, and ASE have all established their own FOWLP packaging technology. FOWLP was originally developed by the German company Infineon. It can, while maintaining the same package size, enable the expanding of the Redistribution Layer (RDL), increase the number of pins, and integrate more functions. Most importantly, this technology eliminates the need for a package carrier (no wires or solder bumps required). At present, FOWLP is used mainly in wireless communication devices, automobiles, smart phones and other diverse fields. It has the ability to replace the more costly TSV process. It can provide the high density signal contacts required by advanced chips while reducing process costs by about 30% in addition to making the wafer thinner. Furthermore, FOWLP packaging technology can be customized according to customer needs, leading to a variety of variations. As such, it has a great deal of potential for market development. According to research institute forecasts, each smart phone in the future will contain more than 10 chips using FOWLP technology. The number of wafers produced could grow by as much as 32%. In addition, the application market of FOWLP will reach a compound growth rate (CAGR) of 15.1% between 2020 and 2026. By the end of 2026, its market size is predicted to increase to 3.425 billion USD.

3D packaging technology is, at present, mostly used to improve the performance of HPC chips. It is commonly found in the chip integration between processors such as high bandwidth memory (HBM) and CPU, GPU, FPGA, and NPU. 3D packaging usually involves vertically stacking all the chips together using TSV interconnection technology, thereby shortening the transmission paths between them and improving the chip’s overall speed and computing capabilities. Currently, in addition to the previously existing packaging and testing factories such as ASE, Powertech, and Amkor, etc., many semiconductor companies, including TSMC, Intel, Samsung, and Micron, are all also actively investing in the development of 3D packaging, competing for industry leadership. At present, one of the most well-known 3D packaging technologies, the SoIC integrated packaging architecture proposed by TSMC, mainly uses W2W and C2W hybrid bonding technology to realize the interconnection of I/O nodes below 10um, reduce parasitic effects, and make the chip thinner as well as to achieve other packaging functions. Then there is the 3D packaging technology called X-Cube that was launched by Samsung in August of 2020. With this technology, 4 SRAMs can be stacked on the logic core computing chip and connected via the TSV structure. The X-Cube packaging has been successfully applied to the 7nm EUV process and is in the process of being verified for use in the next generation 5nm process. Its future application will be in high-end fields such as HPC, 5G, and AI.

In terms of the development of advanced packaging technology, Intel is also moving steadily. It launched a 3D logic chip packaging technology called Foveros in December of 2018. The package architecture makes use of TSV and Micro Bumps to stack and connect different wafers Face-to-Face. At present, Foveros technology can achieve a contact pitch of 50um, and it is anticipated that, in the future, it will be able to reduce the pitch to 10um, resulting in a bump count of 10,000 per square millimeter. Such a high contact density will eliminate the need for Fan-in and Fan-out structure designs for multi-chip integration. Furthermore, the Foveros package is highly scalable. It combines the two core technologies of the company’s own 2D/3D packaging: ODI and CO-EMIB, enabling all-around signal interconnection between all the Chiplets integrated in the package.

As for the Chiplet modular packaging architecture, simply put, it is multiple smaller, homogeneous or heterogeneous chips integrated to form a single large chip. The method is to take circuit elements that were originally part of the same SoC chip design and break them up into many small chip blocks. The Chiplets are first fabricated separately then integrated through advanced packaging processes. The traditional SoC system single chips put all component designs on a single die. Therefore, the more functions a chip has, the larger its size. Adopting the Chiplet packaging architecture, however, enables the dispersing of large, multi-core designs onto numerous individuals of small dies. This not only improves the flexibility of the chip’s functional integration design but can also achieve better process yields. It also has the advantage of lower costs and can reduce the design time required, thus shortening the time it takes for a product to make it onto the market.

The Chiplet packaging architecture was first proposed by Intel and AMD. Its basic concept is similar to that of Lego building blocks. It is versatile and able to flexibly combine various small chips into different IP modules. Therefore, if the industry can standardize interconnection communication specifications for the package architecture then, it would become possible to directly use the IP-module Chiplets provided by the IC design company for combined design and manufacturing when designing high-end SoC chips. The development of Chiplet packaging technology is still at an early stage. In view of the infinite possibilities in its future market applications, in March of 2022, Intel, along with multiple other companies, including ASE, AMD, ARM, Google Cloud, Meta, Microsoft, Qualcomm, Samsung and TSMC, announced the joint establishment of a Chiplet industry alliance and the plan to formulate a standard UCIe (Universal Chiplet Interconnect Express) for transmissions between small chip components to accelerate the establishment of an open global Chiplet packaging ecosystem. In the future, all IC design and Fabless semiconductor companies will be able to use this system pipeline and purchase different IP module chips from each other to easily design and build any custom SoC they desire.

In the past, the development of ICs focused on increasing the number of transistors and integrating more components into one SoC chip to continuously improve chip size and performance. With the shrinking of the semiconductor line width approaching its physical limits, however, Moore’s Law is becoming unsustainable, and global wafer foundries are gradually shifting their development focus from the pursuit of more advanced wafer processes to innovative packaging technologies. Based on the current industry development trend, we can predict that future advanced packaging solutions for 2.5D/3D heterogeneous integration will use the Chiplet modular architecture. Higher performance SoC-SoC chips will be formed through the package integration of standardized SoCs with various functions. The traditional process of using substrate and wire connections will also evolve into the wafer-level packaging Micro Bumps or direct metal-to-metal interconnection technology. With the transformation of the semiconductor industry brought about by advanced packaging and its development for all emerging technology applications will come greater room for imagination.

This article provides a comprehensive introduction to the most advantageous process technology in advanced packaging, “Copper-copper contact interconnection”. After receiving his Ph.D. from the Department of Materials Science at the University of California, Los Angeles (UCLA) in 1999, Professor Zhi Chen has been teaching and conducting research at the Department of Materials Science at Yang Ming Chiao Tung University, where he is currently the head of the department. Professor Chen pioneered the discovery of the (111) nano-twin copper in academia. His research findings were published in the top journal SCIENCE in 2012. He subsequently transferred the technology to domestic manufacturers, leading to successful mass production and essentially helping Taiwanese companies enter the electroplating copper additive market. Professor Chen has made outstanding contributions to this field of research over the years, earning many awards both at home and abroad. In 2020, he was also elected as a fellow of the International Association of Advanced Materials (IAAM). MA-tek is honored to be able to join hands with Professor Chen this year to carry out industry-university collaborations by providing the research team with the full analysis services needed for the research of low temperature copper-copper contact processes. MA-tek has a comprehensive set of testing equipment and the professional technical experience to be able to fully meet the various analysis and testing needs of electronic materials processes and packaging.