The Latest Developments in 3D IC Full-intermetallic Compound Solder Bumps

The development of advanced packaging technology is the biggest driving force behind the semiconductor industry. As the shrinking of the semiconductor line width reaches its physical limit and manufacturing costs continue to soar, relying on Moore’s Law to increase the number of transistors has proven ineffective for reducing costs and increasing profits. Therefore, the focus of wafer foundries around the world is gradually shifting from the pursuit of more advanced wafer processes to innovative packaging technology. At present, many well-known manufacturers, including Intel, TSMC, ASE, and Samsung, are increasing their investments in advanced packaging. Estimates made based on the latest market research say that, between 2020 and 2026, the advanced packaging market will grow substantially at a CAGR of 7.9％, and the global revenue has the opportunity to surpass the scale of 42 billion USD before 2025. Among the various advanced packaging technologies, the three biggest categories are the  2.5D/3D stacked IC, Embedded Die (ED) and Fan-Out (FO), which have CAGRs of 21％, 18％ and 16％ respectively.

Based on the concept that a “multidimensional architecture layout” can greatly increase the interconnection density of contacts, the packaging industry is gradually moving from developing 2D plane to 3D stacking designs and from single chips to different types of multi-chip heterogeneous integration packaging technologies, including the Flip Chip, Bumping, Wafer Level Packaging, 2.5D packaging (Interposer/RDL), 3D packaging (TSV) and more. Furthermore, the Chiplets architecture is expected to become the mainstream structure for these integrated designs.

Advanced packaging technologies can use 2.5D/3D stacking to realize the highly flexible Chiplets design and configuration by integrating IP modules with different functions. This would not only speed up chip development but also greatly reduce R&D and manufacturing costs. For example, under 14nm process conditions, producing ICs using the Chiplets architecture as opposed to the typical System-on-Chip (SoC) design approach can reduce manufacturing costs by more than 50％. Therefore, advanced packaging technologies have become a new blue ocean for the development of the semiconductor industry. The Chiplets design architecture using 2.5D/3D packaging is an inevitable technological trend. As such, how to increase the chip interconnection density and how to achieve extreme heterogeneous integration of various chips will become core competitive advantages in the field of advanced packaging in the future.

Judging from the current development trajectory of advanced packaging, there are two main technical approaches for realizing high-density interconnects with pitches of less than 40μm. One is to continue to reduce the size of traditional solder bump contacts. The other is the development of copper-copper bonding metal interconnection technology. Both of these approaches have the potential to shrink the pitch of chip contacts to 10μm and provide more than 5 million I/O contacts on a 12 inch wafer.

As contact technology gradually moves towards narrower pitches, the challenges to be overcome grow ever more numerous. In terms of manufacturing processes, although copper-copper bonding technology can obtain a smaller pitch size than the direct miniaturization of solder bumps, the technology’s production costs are still too high for most OSATs. Its manufacturing process would also demand the construction of expensive semiconductor fabs. Microbump technology, on the other hand, can make use of existing packaging processes and infrastructure, giving it more advantages in both cost and yield, so it is still the mainstream development trend favored by many major manufacturers. At present, well-known suppliers actively investing in the development of narrow-pitch  μ-bump technology include Amkor, ASE, Intel, JCET, Samsung and TSMC, etc.

Director of R&D Center & Marketing Division, Chris Chen, 2022/10/31

Advanced Packaging Rules! The Latest Developments in 3D IC Full-intermetallic Compound Solder Bumps

Professor  Jenq-Gong Duh, Department of Materials Science and Engineering, National Tsing Hua University

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With the advent of the big data era, the demand for consumer electronics has grown ever more extensive. The rapid rise of technologies such as the Internet of Things, 5G, artificial intelligence and electric vehicles has led to the popularization of products such as robots, unmanned vehicles and drones. The technical requirements of these applications include high speed information transmission, the ability to perceive external environments, and reduced transmission delays while meeting a variety of goals, including saving energy and reducing risks. All of this requires enormous amounts of extremely fast calculations. This has made the demand for advanced semiconductor wafers skyrocket.

As these technologies advance, the density of electrical transistors in chips is getting higher and higher, but the miniaturization of the transistors in VLSI based on Moore’s Law is slowing down. Therefore, the continued increase in transistor density today requires breakthroughs in advanced packaging. The Insight Partners’ (a market research company) February 15, 2022 report, ”Advanced Packaging Market Size, Share, Revenue, Growth, Global Analysis and Forecast to 2028”, showed that, due to innovations in packaging technology, miniaturization of devices and the popularization of MEMS (Microelectromechanical systems), the advanced packaging market will grow at a CAGR of 8%, going from approximately 30 billion USD in 2022 to 55 billion USD in 2028. Advanced packaging accounted for approximately 40% of the semiconductor packaging market in 2020, and it is expected to increase to more than 60% by 2030 (Figure 1). In addition, it is estimated that, between 2021 and 2030, the compound annual growth rate of 3D/2.5D ICs and Fan out packaging will be about 22% and 16% respectively. They are the fastest growing technologies among all advanced packaging technologies (Figure 2)[1].

The increase of transistor density in advanced packaging is mainly being driven by Cu-Cu hybrid bonding and Microbump technology. The former is designed for high-end products with a contact pitch below 10μm. It is able to achieve higher transistor densities. In addition to the Cu-Cu interconnect, there is the Au-Au interconnect. This method is based on the inter-diffusion bonding of flat, pure metals. The manufacturing threshold and difficulty are high, and better surface smoothness and cleanliness are required. The latter is a more common technology on the market and is mainly used in mid to high-end products.

At present, the most advanced Microbump has a pitch of 40μm. As thermal compression bonding (TCB) technology improves and more advanced machine designs emerge, it is possible that Microbump pitch may be reduced to 20μm or even 10μm in the near future. Furthermore, the size of a Microbump is about 50％ of the pitch. This means that Microbumps may reach the sizes of less than 10μm (Figure 3).

Figure 3.　Miniaturization of Bump Pitch and Size [2]

Take, for example, the solder bumps of advanced packaging. The largest BGA diameter is about 760μm. The (C-4) solder joint of the medium-sized flip-chip package is about 100μm. The diameter of the μ-bump in 2.5D/3D IC technology is  10μm (Figure 4). Compared to the C-4 solder bump, the Microbump is 10 times smaller in diameter and has only 1000^th the volume. The increase in the surface area/volume ratio increases the solder-interface reactivity. This makes a huge difference in the microstructure.

Figure 4.　Cross-Sectional View of the 2.5D/3D IC Packaging Structure [3]

In 2.5D/3D ICs, the multi-layer packaging structure and smaller solder bumps means that the packaging process will go through multiple Reflows, causing the rapid growth of intermetallic compounds (IMC) and increasing tin consumption and IMC generation inside the solder joints. As the proportion of IMC in the solder bumps increase, the properties of the grains will significantly affect the physical properties of the solder bump.

Void formation in the microstructure is generally the most common source of concern when evaluating a solder joint’s reliability. Electroplating is one of the processes for depositing solder for small μ-bump packaging with a fine pitch. As with the Cu-pillar bump shown in Figure 3, the growth from the Cu-pillar bump itself to the solder cap can be formed via electroplating.However, electroplating introduces various impurities, such as surface leveling agents, cleaning agents, inhibitors and other foreign metal atoms added to the plating bath, into the solder layer. When more solder is consumed (Figure 5), the concentration of impurities that are insoluble in the IMC increases, and they are pushed to the grain boundaries, forming defects and voids.

In traditional packaging, oxides on the surfaces of solder balls and residual flux can cause similar problems. However, due to the low proportion of IMC in the solder joints, changes in impurity concentrations are comparatively small and less likely to cause harmful effects [6]. As such, the probability that impurities will cause defects will rise with the reduction in size of the solder joints because of the fully IMC solder joints, adversely affecting reliability by causing problems such as the weakening of mechanical strength and the decline of electrical properties due to stress concentration.

Figure 7.　(a) - (d) BEI of Cu/Sn/Cu (10µm) after reacting at 250° for 1, 12, 17 and 20 minutes respectively [6]

Figure 8.　Impurities become concentrated as the IMC grows [6]

In addition to the voids caused by the miniaturization of solder joints, voids can also be caused by a combination of electroplating parameters and the plating bath environment during the electroplating process. Figure 9 shows processes where only PEG and Cl inhibitors were added under P-h (high current density) and P-l (low current density) for solder joint microstructures with a Cu plating. When the current density is reduced and passed through Reflow, a complete and void-free microstructure can be obtained.

Figure 9.　 Solder Joint Microstructure After Plating Coating Reflow Under High and Low h/l Current Densities With PEG and Cl Inhibitors Added [7]

Also see the microstructure of solder joints when accelerators A and B are added under the same electroplating conditions (Figure 10). Accelerator B’s ability to displace PEG inhibitor absorption sites in the electroplating process is poor, and the higher impurity concentration causes voids. Therefore, the adjustment of electroplating parameters and the development of electroplating bath formulas, including current densities and the simultaneous addition of inhibitors and accelerators, is critically important to controlling the size of grains and the generation of voids [7].

Figure 10.　 Microstructure of Solder Joints After Plating Reflow at the Same Current Density with Accelerators A and B Added [7]

Although adjusting the plating parameters and adding inhibitors and accelerators can be helpful to preparing void-free plating, when it comes to 3D ICs, these benefits must be weighed against the defects that might be caused by incorporating additives into the solder joint miniaturization process (due to the increased impurity concentration). Whether to simplify the plating bath formula to reduce impurity sources and how to control the electroplating parameters may be the key challenges for the electroplating process in the 3D IC field.

The additives used in the electroplating process are not always harmful. In addition to their ability to affect the formation of voids after Reflow, they can modify the surface morphology of the coating. This demonstrates their potential application value and flexibility. As shown in Figure 10, by developing plating bath additives and adjusting process parameters, Cu coatings with special surface morphologies can be prepared and applied to fully IMC solder joints. Domed and pyramidal surfaces greatly increase the shear strength of solder joints, and, thanks to the interlocking effect and the riveting of the special Cu surface structures, it is difficult for cracks to propagate and expand [8].

Figure 11.　 Shear Strength of All IMC Solder Joints with Faceted, Domed and Stepped Pyramid Surface Structures [8]

Figure 12.　Domed and Stepped Pyramid Solder Joints – Top View SEM Images of the Fracture Surface: (a) Domed, (b) Stepped Pyramid, and (c) Fracture Path Schematic Diagram [8]

Finer Microbump pitches and smaller volumes of solder materials in the solder bumps mean there is rapid depletion of Sn and massive formations of IMC. Although this greatly improves the possibility of realizing TLPB, it may also result in the formation of voids and affect reliability. There are also reasons other than the influence of impurities in the process for the formation of voids, such as the Kirkendall void caused by the differing diffusion rates of two elements. Take, for example, the common Cu/Sn interface layer. The Cu will first form the Cu6Sn5 phase with the Sn. The Cu6Sn5 phase will then form the Cu3Sn phase with the Cu.   In a room-temperature environment of 300K, the diffusion of Cu in the Cu3Sn phase is 17 times the diffusion rate of Sn atoms in the Cu3Sn phase. Such a large difference in diffusion rates causes the appearance of Kirkendall voids at the Cu/Cu3Sn interface (Figure 13). With the progression of thermal aging, the area of the Kirkendall void will increase with the thickening of the Cu3Sn layer. This has been a key issue at all levels of packaging for a long time.

Figure 13.　SEM Top View of Cu Plating with Various Surface Morphologies: (a) Planar,  (b) Domed, and (c) Stepped Pyramid [8]

Figure 14.　Void at BGA Package Contact Interface [9]

Figure 15.　Diffusion Rates of Cu and Sn in the  Cu3Sn Phase [10]

Regarding the TLPB IMC solder bumps being widely discussed in the 3D IC field, the faster IMC growth rate brought about by the shrinking of solder bumps increases its advantage in terms of manufacturability. On the other hand, the interface reaction that occur in the Reflow and thermal aging processes causes the IMC to grow excessively. It also increases porosity in the contact. Aside from the Kirkendall voids mentioned above, phase inversions due to thermal reactions may cause changes in volume (Table 1). Decreases in volume cause internal stress. As the IMC continues to grow, the occurrence of second phase transitions (such as the Cu6Sn5 Phase transformation into the Cu3Sn phase) all have the potential to increase the internal stress and cause cracks and voids, which are detrimental to reliability.

Table 1.　Volume Change Rate Under Various Reactions [6]

Figure 16.　Volume Shrinkage Stress Caused by Solder and Metal Reaction  (a) As-assembly (b) During the Reaction (c) All Solder is Consumed [6]

In short, IMC generation is a double-edged sword. Due to the IMC’s hard and brittle nature, it may strengthen the mechanical properties of solder bumps if it is used to replace Sn, but it can cause many reliability issues if overgrown. The demand for 3D stacking will continue to grow in the future. The time needed for the TLPB process is several times shorter now than it was in the past, and all IMC solder bumps have become possible due to downscaling. However, how to avoid voids caused by excessive IMC growth under the influence of the thermal effect will become an important issue. The phenomenon of rapid IMC growth did not occur in the large C-4 solder bumps of the past. It is a phenomenon unique to the full IMC solder bump. When the scalloped Cu6Sn5 grains on both sides come into contact (Figure 17), they will quickly coalesce into a columnar grain. This coarsens the grain.   Figure 17. (a) SEI of Cu/Sn/Cu after Reflow for 3 Minutes at 260°C; (b) EBSD Grain Orientation Diagram of Cu6Sn5 (Reflow 3 Minutes); (c) EBSD Grain Orientation Diagram of Cu6Sn5 (Reflow 4 Minutes) [11]

In general, the grain boundary energy depends on the grains’ crystallographic misorientaion. It is speculated that high-angle grain boundaries have higher energies. Scalloped Cu₆Sn₅ undergoes extremely fast grain growth. It is a high-angle grain boundary caused by liquid solder wetting. The liquid channels provide extremely fast kinetic paths for grain growth. If the grain boundary is low-angle, tilted or twisted, however, the liquid solder cannot wet it, so rapid grain growth will not occur [11].

There is also a certain relationship between the difference in grain orientation and grain size, like the BGA solder bump shown in Figure 18 [12], where there is an interfacial reaction between the SAC305 solder ball with added Ni and the OSP Cu substrate. The blue line, red line and black line in Figure (b) represent the grain boundary dislocations of 65゜, between 55 and 65゜, and less than 55゜ respectively. It can be observed in the Figure that the lower grain boundary angle dislocation regions, such as the red and black line areas, usually have denser distributions. The β Tin is also finer and forms interlace structures like the one shown in 17 (a).

Figure 18.　(a) EBSD Grain Orientation Maps of 4 Selected SAC1205-0.1Ni/OSP Cu Solder Bumps; (b) Grain Crystal Misorientation Diagram of the Corresponding SAC1205-0.1Ni/OSP Solder Bumps [12]

Adding a layer of Ni between the Cu/Sn interface to act as a diffusion barrier layer is common in packaging. It can reduce the growth rate of Cu-Sn IMC. It has also been pointed out in the literature that Ni can be used as the nucleation site of Cu₆Sn₅ grains in Sn to promote grain refinement and improve the mechanical properties of solder bumps. It is anticipated that the addition of elements can be applied to the 3D IC’s TLPB solder bump to improve grain refinement, grain orientation diversification and more to enhance the reliability of solder bumps  [13]. In addition, compared to (Cu,Ni)₆Sn₅, (Cu,Ni)₆Sn₅ on the (001) and (110) crystal planes have more similar properties and strength [14], and solid solution strengthening improves the hardness of the grains themselves.

Past studies have also confirmed the short-range order caused by the addition of Zn. It can refine the grains and diversify their orientations [15-17] (Figure 19). In TLPB solder bumps, the addition of Zn will make the Cu₆Sn₅ grains form interfold microstructures, as shown in Figure 20(d). Modification of preferred orientation grains into interfold microstructures can potentially improve solder bump reliability by reducing crack propagation paths [16].

Adding Zn to the substrate helps improve the phase stability of Cu₆Sn₅, preventing its conversion into the Cu₃Sn phase and the accompanying Kirkendall voids [18-20]. As shown in Figure 21, after thermal aging, substrates with added Zn are almost completely free of the growth of Cu₃Sn and Kirkendall voids. This demonstrates the good thermal stability of Cu₆(Sn,Zn)₅.

Figure 21.　Cross-Sections of Sn/Cu, Sn/Cu-15Zn and Sn/Cu-30Zn Solder Bumps (a) - (c) Before Thermal Aging; (d) - (f) Cross-Sections After Thermal Aging at 150゜C for 80 Days [18]

Figure 22 below is a cross-section of the Ni/SnACu/Cu1-x -Zn x solder joint microstructure. Adding Zn to the Cu substrate completely suppresses the Cu₃Sn phase in the substrates on both sides. Although these studies were of the interface reactions of BGA solder joints, the good IMC growth inhibition and phase stability meet the LPB Microbump’s need to prevent the excessive growth of IMC. As such, it has great potential application value in the future 3D IC field.

Figure 22.　Interface Microstructure of (a) Ni/SnAgCu/Cu, (b) Ni/SnACu/Cu-15Zn, and (c) Ni/SnAgCu/Cu-30Zn [20]

Over the next few years, the market demand for advanced packaging and 3D ICs will continue to grow rapidly. The miniaturization of solder bumps has enabled the realization of full IMC Microbumps prepared using the TLPB process. Due to the high melting point of the solder and the complete consumption of the Sn, it can avoid the alignment and stacking problems caused by the re-melting of Sn after multiple Reflows. However, there are several key problems facing TLPB, including the rapid and excessive growth of IMC and the accompanying volume shrinkage, voids caused by phase changes and the Kirkendall effect, and voids caused by impurities generated by the electroplating process. These and other issues emerge one by one once the Microbump becomes fully occupied by the IMC. Fortunately, by adjusting the plating bath environment and electroplating parameters, the possibility of defects caused by the electroplating process can be significantly reduced.

By doping the metal substrate with various elements, we expect not only to modify the grain sizes and orientations of the IMC but even to improve its thermodynamic stability. Then, through prolonged thermal aging, we can prevent volume shrinkage and voids caused by phase transitions. If determined to be suitable for application to the Microbump of the 3D IC, it is expected to greatly improve the long-term reliability of these Microbumps.

Reference: 

[1]https://www.globenewswire.com/en/newsrelease/2022/02/15/2385153/0/en/Advanced-Packaging-Market-Worth-55-Bn-Globally-by-2028-at-8-CAGR-Exclusive-Report-by-The-Insight-Partners.html

[2]Ramalingam, Suresh. "Advanced Packaging–Future Challenges." CMC Conference. 2016.

[3]T. L. Yang , et al. "Effects of silver addition on Cu–Sn microjoints for chip-stacking applications." Journal of alloys and compounds 605 (2014): 193-198.

[4]Sun, Lei, et al. "Recent progress in SLID bonding in novel 3D-IC technologies." Journal of Alloys and Compounds 818 (2020): 152825.

[5]Yang, Ting Li, et al. "Full intermetallic joints for chip stacking by using thermal gradient bonding." Acta Materialia 113 (2016): 90-97.

[6]H. Y. Chuang,, et al. "Critical concerns in soldering reactions arising from space confinement in 3-D IC packages." IEEE Transactions on Device and Materials Reliability 12.2 (2012): 233-240.

[7]Lee, Hsuan, Wei-Ping Dow, and Chih-Ming Chen. "Effects of additive formula and plating current density on the interfacial reactions between Sn and Cu electroplated layer." 2016 International Conference on Electronics Packaging (ICEP). IEEE, 2016.

[8]Hsu, Shao-Yu, et al. "Surface modification of Cu electroplated layers for Cu–Sn transient liquid phase bonding." Materials Chemistry and Physics 277 (2022): 125621.

[9]Mei, Zequn, et al. "Kirkendall voids at Cu/solder interface and their effects on solder joint reliability." Proceedings Electronic Components and Technology, 2005. ECTC'05.. IEEE, 2005.

[10]Gao, Feng, and Jianmin Qu. "Calculating the diffusivity of Cu and Sn in Cu3Sn intermetallic by molecular dynamics simulations." Materials Letters 73 (2012): 92-94.

[11]Gusak, A. M., King-Ning Tu, and Chih Chen. "Extremely rapid grain growth in scallop-type Cu6Sn5 during solid–liquid interdiffusion reactions in micro-bump solder joints." Scripta Materialia 179 (2020): 45-48.

[12]Fleshman, Collin, and Jenq-Gong Duh. "The Variation of Microstructure and the Improvement of Shear Strength in SAC1205-xNi/OSP Cu Solder Joints Before and After Aging." Journal of Electronic Materials 49.1 (2020): 196-201.

[13]H. J. Dong,et al. "Grain morphology evolution and mechanical strength change of intermetallic joints formed in Ni/Sn/Cu system with variety of transient liquid phase soldering temperatures." Materials Science and Engineering: A 705 (2017): 360-365.

[14]D. Mu , H. Huang, and K. Nogita. "Anisotropic mechanical properties of Cu6Sn5 and (Cu, Ni) 6Sn5." Materials Letters 86 (2012): 46-49.

[15]Wei-Yu Chen, and Jenq-Gong Duh. "Suppression of Cu3Sn layer and formation of multi-orientation IMCs during thermal aging in Cu/Sn–3.5 Ag/Cu–15Zn transient liquid-phase bonding in novel 3D-IC Technologies." Materials Letters 186 (2017): 279-282.

[16]Wei-Yu Chen, Rui-Wen Song, and Jenq-Gong Duh. "Grain structure modification of Cu-Sn IMCs by applying Cu-Zn UBM on transient liquid-phase bonding in novel 3D-IC technologies." Intermetallics 85 (2017): 170-175.

[17]Wei-Yu Chen, et al. "Growth orientation of Cu–Sn IMC in Cu/Sn–3.5 Ag/Cu–xZn microbumps and Zn-doped solder joints." Materials Letters 134 (2014): 184-186.

[18]Chi-Yang Yu, and Jenq-Gong Duh. "Growth mechanisms of interfacial intermetallic compounds in Sn/Cu–Zn solder joints during aging." Journal of Materials Science 47.17 (2012): 6467-6474.

[19]Chi-Yang Yu, Wei-Yu Chen, and Jenq-Gong Duh. "Improving the impact toughness of Sn–Ag–Cu/Cu–Zn Pb-free solder joints under high speed shear testing." Journal of alloys and compounds 586 (2014): 633-638.

[20]Chi-Yang Yu,Wei-Yu Chen, and Jenq-Gong Duh. "Suppressing the growth of Cu–Sn intermetallic compounds in Ni/Sn–Ag–Cu/Cu–Zn solder joints during thermal aging." Intermetallics 26 (2012): 11-17.

For nearly half a century, the semiconductor industry has developed following the predictions of Moore's Law and become a technology industry with a pivotal position in the global economy. However, with the successful advancement of semiconductor processes from the 7nm to the 5nm and the active movement towards the 2nm node, it is growing ever more difficult to maintain Moore’s Law. There are two main problems. One is the problem of costs and investments. The other is the technical challenge inherent in size reduction. Though semiconductor chip manufacturers can continue to compress transistor sizes, the cost of making advanced chips is skyrocketing. So, in terms of average yield, this tactic is no longer cost effective. For example, at present, the distinction between chips with mature processes and advanced processes is typically drawn at the 28nm mark. Just between the 5nm and 8nm logic chips, there is a difference in manufacturing cost of nearly 10 times. If the cost effectiveness was considered only in terms of the increased number of transistors, there is no longer any benefit to be gained from mere size reduction.

It costs tens of billions of USD to construct a fab for processes below 7nm, and that would not even include the subsequent operation, maintenance, technology research and development and other expenses. So, at present, there are only three manufacturers in the world who have the ability to continue to participate in the advanced process competition: TSMC, Samsung and Intel. In addition, as the wafer size shrinks to 1nm, leakages, heat generation and serious power consumption caused by short-channel effects are also limitations that have thus far been difficult to solve.

With the rise of emerging technologies such as AI (artificial intelligence), 5G communications, the Internet of Vehicles, the Metaverse, and Industry 4.0, the demand for high speed computing is increasing exponentially. Even if the transistor is miniaturized to its physical limits to improve performance, it would remain far from being able to meet the needs of future industrial applications. Therefore, in recent years, researchers have turned to packaging technology in search of new solutions in the hopes of continuing the perpetuation of Moore’s Law and providing the chip computing performance required for the innovative industrial applications of the future.

Advanced packaging technology provides a cost-effective way to achieve the goal of high density contact interconnections and heterogeneous chip integration. Whether it’s to continue or surpass Moore’s Law, advanced packaging technology will be essential. Therefore, those in the supply chain of the global semiconductor industry, including major fabs, packaging and testing companies, and even some slightly larger Fabless companies, are all increasing their investments in advanced packaging. The leading foundry TSMC has always led the way. Aside from its 4 existing packaging and testing factories, including Tainan Science Park, Taichung Science Park and Longtan, it will also be opening a 5^th packaging and testing factory, the AP6 in Zhunan, for mass production in the second half of this year to provide advanced packaging foundry services, including SoIC, WoW, and CoW. ASE, the leader in packaging and testing, also announced last June that it would be investing 2 billion USD into boosting its wafer packaging business. In September this year, UMC and the packaging and testing manufacturer Chipbond planned to exchange equities to strengthen their long-term, strategic cooperation in the field of advanced packaging. In addition, according to reports by the South Korean media, Samsung is evaluating a plan to invest about 200 billion Korean won into the expansion of its semiconductor fab in Cheonan, South Korea to establish its advanced fan-on-wafer-level-packaging (FOWLP) production line.

Based on current industry trends, it can be predicted that future 2.5D/3D heterogeneous integration advanced packaging solutions will embrace the Chiplets architecture. When the number of defect points within a wafer is roughly fixed, using the Chiplets design can drastically reduce the number of ICs affected by defects, thus improving wafer yield and reducing manufacturing costs. Chiplets have not only a high degree of design flexibility but also the advantages of high yield rates and reasonable process costs. This has led many semiconductor manufacturers to invest in its development. AMD is considered the leader of Chiplet packaging architecture development. It fully adopted Chiplets technology in 2019 and has successfully applied it to the commercial production of Ryzen and Epycx86 processors. In the same year, Huawei in mainland China launched its 7nm kumpeng 920 processor based on the Chiplets design. Also, in March of this year, Apple joined hands with TSMC to launch its “monster chip”, the M1 Ultra, which adopted TSMC’s own CoWos-S Chiplets design architecture and caused a sensation in the market. In addition, due to adjustments in the global semiconductor inventory, many major semiconductor equipment manufacturers have successively signaled that growth will slow next year. However, TSMC, Intel and ASE’s endeavors in advanced packaging technology forge on. TSMC President Zhejia Wei recently stated that advanced packaging will be the next catalyst for the company’s growth. It is estimated that it will have an annual growth of 20%. They will emphasize the packaging architecture and innovation required to realizing the 2.5D/3D Chiplets design that will be one of the keys to promoting the continuation of Moore’s Law in the semiconductor industry over the next few years.

This article provided a comprehensive overview of the research and development of the highly anticipated Microbump technology of the advanced packaging field. The author, Professor Jenq-Gong Duh, has been teaching in the Department of Materials Science and Engineering at Tsing Hua University since obtaining his Ph.D. from Perdue University in 1983. During this period, he served successively as the provost of Tsing Hua University, the convener of the Materials Science Department of the National Science Council, and the chairman of the Taiwan Coating Technology Association, etc. and earned the Tsing Hua University Outstanding Teaching Award, the National Science Council Outstanding Research Award and other honors. He has made great contributions to the domestic academic development.

Professor Duh has devoted himself to the academic research of electronic packaging, thin film materials, plasma technology and various energy materials for many years. His team has published more than 460 articles on important research findings in internationally renowned journals, and he holds more than 25 technical patents. His academic achievements are truly outstanding. MA-tek is honored to be able to carry out our second industry-university collaboration project with Professor Duh this year and provide the complete analysis services needed by his team for advanced packaging technology research. MA-tek has a comprehensive set of testing equipment and the professional testing experience to fully meet the various electronic materials, manufacturing processes and packaging analysis and testing needs.