Board Level Reliability Service
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Technical Concept |
The reliability of the printed circuit board with surface-mounted components is referred to Board Level Reliability which is to discuss the reliability of solder bonding between packaging elements and printed circuit board.
With the rapid development of technology, portable electronic products are tended to be light, thin, short, and multi-function. The rising awareness of environmental protection has brought to lead- and halogen-free processing. Due to the new soldering, the material is hard and brittle, and the quality and reliability of the solder joint are facing increasingly tough challenges. This brings more attention to the board level reliability test by the industry.
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Five-level packaging technology for electronic package |
Packaging is a technology based on the establishment of interface interconnections between various levels. As shown in the figure below, the process technology is divided into five different levels：
- Zero level package（Single chip module）─ Circuit design and manufacturing on IC chips.
- First level package（Multichip module）─ Package the IC chip shell and complete the circuit and sealing protection process, also known as Module or Chip-level Packages.
- Second level package（PCB or card）─ The process of combining the packaged components on the circuit card.
- Third level package（Mother board）─ The process of combining several circuit boards on the motherboard, and becoming a subsystem.
- Forth level package（Electronic product）─ The process of combining several subsystems into a comprehensive electronic product (Gate).
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Daisy Chain Design |
In order to monitor the quality of solder joint during the board level reliability test, a daisy chain is implemented. After assembly, solder joints between components and PCB are connected via daisy chain layout to form a network. Using electrical test through the daisy chain to check either the solder joint network is electrically opened or shorted. The failure of solder joints can be localized.
MA-tek can help our customers to design the layout based on JESD22-B111, JESD22-B113, or IPC-9701 standards. Layout examples are shown below.
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Layout example of a Daisy chain |
The appearance of the PCB based on JESD22-B111 standard |
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Board Level Thermal Cycling Test |
To assess the latent effect of thermal fatigue and plastic deformation on the solder joints of surface-mounted components under a temperature cycling environment. Based on the result, the thermal fatigue lifetime of the solder joints is evaluated.
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Real-time resistance measurement curve |
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Board Level Drop Test |
To assess the quality of the surface-mounted components in a portable electronic system under the accelerated environment during falling. The excessive bending of the circuit board is easily leading to product failure.
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Board Level Monotonic Bend Test |
The breaking strength of the board and solder joints are measured by using a monotonic bending load.
IPC-9702 testing |
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Board Level Cyclic Bend Test |
To assess surface mounted components in a circuit board during the practical application which experiences some fatigue bending effects, such as keystrokes on the phone. The bending aging on the solder joint is evaluated.
JESD22-B113 testing |
Cyclic bend test curve |
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Strain Measurement |
Strain Measurement: To measure the strain and strain rate of the SMT package during the PWB assembly, testing, and operation.
 Deformed by an external force |
Schematic diagram of Strain Measurement |
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Vibration Test |
To simulate the vibration of the SMT product during ground transportation of the product or operation. The mechanical vibration will accelerate the deterioration of the defect inside the assembly and further result in the failure of the components.
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